1. Field
The present invention relates generally to electronics circuits, and more specifically to memory architectures and techniques that support direct memory swapping between NAND Flash and SRAM with error correction coding.
2. Background
Newer generation wireless communication devices (e.g., terminals, handsets, and cellular phones) are capable of providing various types of communication such as voice and packet data. Some of these devices may also be designed with enhanced functionality, and may further be operated as a personal digital assistant (PDA), a Web terminal, a computing device, and so on. Newer designs for these devices need to provide all the required functions and features while at the same time conforming to other design constraints such as reduced size, cost, and power consumption.
As wireless communication devices become more complex and are required to provide more functions and features, more computing power and larger memories are inevitably required. A large memory is typically needed to provide storage for data and program codes used to support voice and/or data communication and other functions and features. Various types of memory may be used for these devices, including static random access memory (SRAM), dynamic RAM (DRAM), and Flash.
SRAM and DRAM are volatile memories that lose the data stored therein once power is removed. SRAM and DRAM can be accessed in a random manner, which is the manner most processors are programmed to access memory for data and codes. Consequently, SRAM or DRAM is commonly used as the main run-time storage unit in many wireless communication devices.
Flash is a non-volatile memory that can retain the data stored therein even after power is removed. NAND Flash, which is one type of Flash, is a high-density design and has certain advantages over other types of memory, including a large storage capacity (e.g., one giga-bits or more), good speed for continued access, and low cost. However, NAND Flash also has several inherent drawbacks, including poor performance for random access and increased susceptibility to bit errors over the NAND Flash""s operating lifetime. In particular, NAND Flash is typically accessed in unit of pages, one page at a time, with each page being of a particular size (e.g., 512 bytes).
As the cost of memories in communication devices becomes more prohibitive, NAND Flash is a good candidate for use as the mass storage unit for these devices. However, because the structure of NAND Flash is not suitable for random access, program codes cannot be executed directly from the NAND Flash. Instead, SRAM may be used as an intermediate storage for data and program codes that need to be accessed in a random manner by the processor. A memory architecture that incorporates both SRAM and NAND Flash may thus provide large storage capacity, reduced cost, and random access.
Conventionally, reading data from or writing data into NAND Flash requires excessive involvement and control by the processor. This can tie up the processor and prevents it from performing other functions, which can then result in overall performance degradation for the communication device. Moreover, since NAND Flash is more prone to bit errors, a mechanism is needed to ensure data integrity when loading data from or into the NAND Flash.
There is therefore a need in the art for memory architectures and techniques that can provide improved data transfer for the NAND Flash and which can furthermore ensure data integrity.
In an embodiment, a memory architecture is provided for use in a wireless communication device (e.g., a terminal, a cellular phone, and so on). The memory architecture includes (1) a first storage unit (e.g., an SRAM) operative to provide storage of data, (2) a second storage unit (e.g., a NAND Flash) operative to provide (mass) storage of data, (3) an EMI unit implemented within an ASIC and operative to provide control signals for the two storage units, and (4) a data bus coupled to the first and second storage units and to the EMI unit. The first and second storage units are implemented external to the ASIC, and each storage unit is operable to store data from the other storage unit via the data bus when the other storage unit is being accessed by the EMI unit. The EMI unit may include an ECC unit operative to perform block coding of data retrieved from or stored to the second (NAND Flash) storage unit. The EMI unit may further include an address generator operative to provide addresses for data retrieved from or stored to the first (SRAM) storage unit.
Another embodiment provides a memory system for a wireless communication device. The memory system comprises (1) an SRAM storage unit operative to provide storage of data, (2) a NAND Flash storage unit operative to provide additional storage of data, (3) an interface unit implemented within an ASIC and operative to provide control signals for the SRAM and NAND Flash storage units, and (4) a data bus coupled to the SRAM and NAND Flash storage units and the interface unit. The SRAM and NAND Flash storage units are implemented external to the ASIC, and each storage unit is operable to concurrently store data from the other storage unit via the data bus when the other storage unit is accessed by the interface unit.
Yet another embodiment provides a wireless communication device comprising (1) an external memory unit including an SRAM storage unit and a NAND Flash storage unit, (2) an ASIC including an interface unit operative to provide control signals for the SRAM and NAND Flash storage units, and (3) a data bus coupled to the SRAM and NAND Flash storage units and the interface unit. The SRAM and NAND Flash storage units are each operable to concurrently store data from the other storage unit via the data bus when the other storage unit is accessed by the interface unit.
Yet another embodiment provides a method for transferring data between two storage units in a wireless communication device. Initially, a start address for an SRAM storage unit and a page address for a NAND Flash storage unit are received. Control signals are then provided for the SRAM and NAND Flash storage units in response to receiving a start command. Data is then retrieved from a xe2x80x9csourcexe2x80x9d storage unit, which is either the SRAM or NAND Flash storage unit, via a data bus. The retrieved data is written to a xe2x80x9cdestinationxe2x80x9d storage unit, which is the other storage unit, via the data bus concurrently with the reading of the data from the source storage unit.
Various aspects and embodiments of the invention are described in further detail below. The invention further provides memory architectures, receiver units, wireless communication devices, methods, and other apparatuses and elements that implement various aspects, embodiments, and features of the invention, as described in further detail below.